SystemVerilog

Safer RTL, interfaces, assertions, coverage and modern verification foundations.

1. 01What SystemVerilog Adds to VerilogUnderstand the role of SystemVerilog and select useful features for RTL design and verification.Read
2. 02Types, Widths, and Signed ValuesUse logic, 2-state and 4-state types, sized literals, and conversions without surprises.Read
3. 03always_comb, always_ff, and always_latchChoose the right procedural block and avoid multiple drivers, unintended latches, and sensitivity mistakes.Read
4. 04typedef, Enumerations, and PackagesGive types a clear meaning, encode states cleanly, and share declarations without hidden dependencies.Read
5. 05Arrays, Structures, and UnionsDistinguish packed and unpacked dimensions, group fields, and choose a representation that fits the hardware.Read
6. 06Functions, Tasks, and ScopeFactor calculations and test sequences without hiding dependencies or mixing RTL with timing controls.Read
7. 07Interfaces and ModportsGroup protocol signals, define each block's role, and reduce connection mistakes.Read
8. 08State Machines and Control/Datapath SeparationWrite a readable FSM with an enumerated type and separate decisions from data calculations.Read
9. 09Parameterized and Reusable RTLParameterize widths and types, protect corner cases, and generate hardware without making a module opaque.Read
10. 10Reading a Complete Small RTL DesignReview a packet counter from its interface through corner cases, then connect the code to expected hardware.Read
11. 11Writing a Simple Verification PlanTurn a specification into features to check, corner cases, verification methods, and completion criteria.Read
12. 12Building a Self-Checking TestbenchGenerate a clock, apply cases, calculate expected results, and stop simulation on a real failure.Read
13. 13Dynamic Arrays, Queues, and Associative ArraysChoose a testbench collection for variable batches, transaction queues, and indexed results.Read
14. 14Classes, Inheritance, and PolymorphismModel test transactions, understand handles, and extend behavior without copying an entire environment.Read
15. 15Constrained Randomization and ReproducibilityGenerate varied protocol-correct transactions and reproduce a failure exactly.Read
16. 16Threads, Events, Mailboxes, and SemaphoresRun several testbench activities in parallel and choose the right synchronization mechanism.Read
17. 17Driver, Monitor, Reference Model, and ScoreboardSeparate command driving, DUT observation, prediction, and result comparison.Read
18. 18Immediate Assertions and SVACheck a local condition, express a rule across cycles, and disable properties cleanly during reset.Read
19. 19Functional Coverage and Completion CriteriaMeasure planned scenarios, cross important conditions, and close holes without confusing activity with correctness.Read
20. 20Introduction to UVMUnderstand the components of a UVM environment and when the methodology adds value over a simple SystemVerilog testbench.Read