FPGA Careers

Synthesis turns VHDL or Verilog into a netlist made of logic resources. Implementation then places those resources inside the FPGA, routes them and checks timing. The tool can generate the bitstream after those steps.

A flip-flop stores its input on a clock edge. A latch stays transparent while its enable signal is active. Synchronous FPGA designs mainly use flip-flops and generally avoid unintended latches.

Synthesis unrolls the loop and repeats the requested hardware. It is not a loop executed several times by a processor. A loop with eight iterations may therefore create eight pieces of parallel logic, depending on its contents.

With inference, you write RTL and let the tool recognise the resource, such as a block RAM. With instantiation, you directly use a vendor primitive. Inference is usually more portable, while instantiation gives tighter control over a specific resource.

A flip-flop can become metastable when its input changes too close to a clock edge. A two-flop synchroniser is common for a one-bit control signal. A bus or data stream needs a handshake or an asynchronous FIFO instead.

Block RAM is a physical memory resource inside the FPGA. A FIFO describes how data is stored and read: first in, first out. A large FIFO may use block RAM as its storage.

Both are volatile. DRAM needs regular refresh but provides much more capacity at a lower cost. SRAM is simpler and faster to access but uses more area. External DRAM is commonly used for large amounts of data.

A PLL creates one or more clocks from an input clock. It can multiply or divide the frequency and adjust the phase. Those generated clocks must then be described correctly in the timing constraints.

A flip-flop input must be stable for a short time before the clock edge: that is setup time. It must also remain stable for a short time afterwards: that is hold time. Breaking either requirement can lead to a wrong value or metastability.

Moore outputs depend only on the current state. Mealy outputs depend on both the current state and the inputs. A Mealy machine can react sooner, but its outputs may need more care.

A LUT is a small truth table that implements a logic function. FPGAs also contain flip-flops, internal memories, DSP blocks, PLLs, I/O resources and sometimes high-speed transceivers or embedded processors.

An FPGA is useful for parallel work, predictable timing, high data rates and reprogrammability. A processor is easier for frequently changing software. An ASIC can be faster and more efficient at high volume, but it costs far more to design.

A SERDES converts parallel data into a fast serial stream and performs the reverse operation at the receiver. It is used by interfaces such as PCI Express, Ethernet and SATA. At those speeds, clocks, PCB layout and constraints matter a great deal.

They are dedicated hardware blocks for fast multiplication, addition and accumulation. They are widely used in filters, image processing and fixed-point calculations while saving LUT resources.

A variable takes its new value immediately inside the process. A signal is updated after the process suspends, during a delta cycle. This matters when assignments follow one another because reading a signal still returns its previous value. The hardware produced still depends on the whole piece of code, not only on the assignment operator.

If an output is not assigned in every possible case, it has to keep its previous value. The tool therefore adds storage, which means a latch. Give every output a default value and cover every branch of each if and case statement. In VHDL 2008, process(all) also prevents signals from being left out of the sensitivity list.

Reset can be asserted immediately, but releasing it close to a clock edge may make some flip-flops restart before others or become metastable. A common approach is asynchronous assertion followed by synchronous release. Each clock domain needs its own reset synchroniser.

It means that a path misses the required margin. For setup, the data arrives too late; for hold, it changes too early. Before changing the RTL, check that clocks and constraints are correct, then find out whether the problem comes from too much logic, routing, fanout or an incorrect clock-domain crossing.

The register splits one long combinational path into shorter paths. The design can often run at a higher clock frequency and accept more data back to back. The trade-off is extra latency, more registers and the need to keep control signals aligned with the data.

A two-flop synchroniser is not always enough because the slower domain may never sample a narrow pulse. The pulse can be stretched, converted into a toggle, or sent through a handshake. The destination then rebuilds a one-cycle pulse, and an acknowledgement prevents events from being lost when they arrive close together.

Multiplying N-bit and M-bit values can require up to N + M result bits. If fewer bits are kept, you must decide which bits are removed and how overflow is handled. Fixed-point designs must also track the binary-point position and make truncation, rounding or saturation an explicit choice.

Adjacent Gray-code values differ by only one bit. When a pointer enters the other clock domain, this reduces the risk of sampling an inconsistent mix of several changing bits. The pointers still need synchronisation, correct constraints and careful comparison to produce the full and empty flags.

It supplies part of the current locally during a fast transition and limits rail variation. A long trace or loop adds inductance, so placement matters as much as value. I start with the device recommendations and then measure the rail near the load.

First compare the electrical levels on both sides. Maximum low output must stay below VIL and minimum high output above VIH under the intended current load. I also check FPGA bank voltage, I/O standard, and whether level translation is needed.

Before applying power, I inspect assembly and measure resistance from each rail to ground. I start with a cautious current limit, then check current, rails, clock, reset, configuration, and JTAG in that order. If a rail is wrong or a part heats quickly, I remove power and find the cause.