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Logic gates, Boolean algebra, combinational and sequential logic, timing and metastability.
Syntax, types, signals, processes, FSMs and testbenches, from entity to complete circuit.
Modules, combinational and sequential logic, synthesis and testbenches in Verilog.
Safer RTL, interfaces, assertions, coverage and modern verification foundations.
Internal architecture, LUTs, BRAM, DSP, synthesis, implementation and timing analysis.
Power rails, decoupling, I/O banks, signal integrity, routing and board bring-up.
AXI, AXI-Lite, AXI-Stream and other FPGA and SoC interconnect interfaces.
PS and PL architecture, Vivado, Vitis, bare-metal software, Linux and AXI communication.