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Short chapter quizzes with maximum XP on the first try and detailed feedback after the correct answer.
Quizzes
88
Done
0
Questions
547
AND, OR, NOT, NAND, NOR, XOR and their truth tables.
Identities, theorems, simplification of logical expressions.
D flip-flops, registers, counters, metastability.
Weighted codes, Gray, Excess-3, parity and Hamming.
Minterms, maxterms, Gray adjacency and logic simplification.
Binary, decimal, hexadecimal, octal, bit weights and bus notation.
PISO/SIPO registers, synchronous counters, modulo counters and terminal-count signals.
Parity, syndrome, Hamming and correction limits.
Origins, uses and role of VHDL in the FPGA flow.
Entity, architecture, libraries and ports of a VHDL module.
Telling apart memoryless (combinational) and clocked (sequential) logic.
std_logic, std_logic_vector, integer, unsigned, signed and conversions.
Logical operators, arithmetic, mod/rem, shifts, concatenation and precedence rules.
Differences between signal, variable and constant: scope, update timing, synthesis.
Naming conventions, code organization and classic pitfalls.
Sensitivity list, sequential vs combinational, latches, process(all).
Three classic ways to write a MUX and what they imply for synthesis.
Picking synthesis and simulation tools depending on the target.
Building a hierarchical design: declaration, instantiation, port map.
Testbench structure, clock generation, stimuli, assertions.
Moore vs Mealy, state encoding, one- or two-process style.
std_logic_1164, numeric_std, std.env, textio and practical simulation functions.
Width parameters, generic map, for generate and conditional generation.
Packages, package body, functions, procedures and shared types.
'length, 'range, 'high, 'low, 'event and synthesis attributes.
Elaboration, simulation, synthesis, CDC, latency and advanced genericity.
ufixed, sfixed, Q format, resize, conversions and synthesis limits.
Described hardware, parallel operation, simulation and synthesis.
Interfaces, signals, instances and design hierarchy.
Widths, vectors, concatenations, operators and signed values.
Continuous assignments, combinational blocks and complete path coverage.
Clock edges, reset, enable and nonblocking assignments.
Priority, `case`, default values and unintended storage.
Instance configuration, internal constants, and hardware generation.
Reusable calculations, test tasks, and synthesizable repetition.
State register, transitions, outputs, and FSM verification.
Memory inference, synchronous reads, and FIFO handling.
Stimulus, events, nonblocking assignments, and self-checking tests.
Inferred circuit, pipelining, widths, and timing constraints.
RTL, verification, and the role of SystemVerilog additions.
Logic states, widths, extensions, and conversions.
Combinational logic, flip-flops, latches, and assignments.
Shared declarations, typed states, and dependencies.
Dimensions, named fields, and shared views.
Subroutines, simulation time, and dependencies.
Protocol grouping, roles, and connections.
Current state, transitions, outputs, and datapath.
Parameters, corner cases, types, and generation.
Handshake, accumulation, corner cases, and inferred hardware.
Requirements, scenarios, checks, and completion criteria.
Reference, comparison, sampling, and summary.
Dynamic arrays, queues, and associative indexes.
Objects, handles, inheritance, and virtual methods.
Constraints, distributions, failures, and reproducibility.
fork, events, mailboxes, and semaphores.
Driver, monitor, reference, and scoreboard.
Local conditions, temporal properties, and reset.
Coverpoints, bins, crosses, and closure.
Components, phases, factory, and methodology choice.
LUTs, flip-flops, BRAMs, DSPs, interconnects and I/Os.
Synthesis, mapping, place, route and bitstream.
Visual IP assembly, VHDL packaging, SoC integration.
Latency, throughput, critical path, registers and temporal verification.
Setup, hold, slack, critical path, timing constraints.
Zynq architecture, PS-PL communication over AXI, embedded design.
SAR ADC, R-2R DAC, comparator and digital sequencing.
Asynchronous serial link: start bit, data, parity, stop, baud rate.
Synchronous serial bus: MOSI, MISO, SCLK, CS, modes 0-3.
Two-wire open-drain serial bus, 7-bit addressing, ACK, start and stop.
Open-source SoC bus: master/slave, cycles, handshake.
Intel/Altera bus family: Avalon-MM, Avalon-ST.
ARM AMBA memory-mapped bus: 5 channels, bursts, IDs, VALID/READY handshake.
Simplified AXI variant: single-beat transactions, no bursts, ideal for register access.
AXI streaming variant: single channel, no address, for DSP / video.
PS, PL, Zynq families and hardware-software partitioning.
Block Design, addresses, validation and XSA export.
Platform, BSP, xparameters and GPIO drivers.
APU, RPU, OCM, TCM, DDR and cache coherency.
AXI ports, control, DMA, clocks, resets and interrupts.
Platform, domain, BSP and driver levels.
Source, GIC, ISR and latency.
Buffers, cache coherence and ELF sections.
BootROM, FSBL, U-Boot and BOOT.BIN.
ILA, software debugger and cross-trigger.
Registers, packaging and driver.
Kernel, Device Tree, GPIO and DMA.
Agents, transactions and protocol verification.
Platform, BSP, build and execution on the board.