Chargement…
Chargement…
Start from software code and compare it with several RTL schematics. The goal is to choose the architecture that exactly preserves priorities, conditions, and registers.
0/9 exercises completed
Find the correct schematic - Asynchronous SRAM Controller
VerilogIdentify the state machine that stabilizes address and data around an SRAM access cycle.
Find the correct schematic - Burst DMA Controller
VerilogTrace the read/write alternation and address updates of a DMA transfer.
Find the correct schematic - VeSPA Hazard Unit
VerilogIdentify forwarding comparators and load-use hazard detection in a pipeline.
Find the correct schematic - DRAM Refresh Decision Unit
VerilogAnalyze the Verilog code for dram refresh decision unit.
Find the correct schematic - Fast-page DRAM Command
VerilogAnalyze the Verilog code for fast-page dram command.
Find the correct schematic - Urgent Memory Arbiter
VerilogAnalyze the Verilog code for urgent memory arbiter.
Complete the 5th SW→HW exercise
Find the correct schematic - Cache Write-policy Unit
VerilogAnalyze the Verilog code for cache write-policy unit.
Complete the 5th SW→HW exercise
Find the correct schematic - DMA Descriptor Address
VerilogAnalyze the Verilog code for dma descriptor address.
Complete the 5th SW→HW exercise
Find the correct schematic - Binary16 Floating-point Classifier
VerilogAnalyze the Verilog code for binary16 floating-point classifier.
Complete the 5th SW→HW exercise