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Start from software code and compare it with several RTL schematics. The goal is to choose the architecture that exactly preserves priorities, conditions, and registers.
0/9 exercises completed
Find the correct schematic - PAL Chip-select Decoder
VerilogMatch partial decoding of the four most-significant address bits to its logic diagram.
Complete the 5th SW→HW exercise
Find the correct schematic - Two-digit BCD Adder
VerilogIdentify the decimal adder datapath that corrects each digit when its sum exceeds nine.
Complete the 5th SW→HW exercise
Find the correct schematic - Dual-priority Encoder
VerilogInfer the network that successively extracts the two lowest-index active requests.
Complete the 5th SW→HW exercise
Find the correct schematic - Four-digit BCD Sanitizer
VerilogAnalyze the Verilog code for four-digit bcd sanitizer.
Complete the 5th SW→HW exercise
Find the correct schematic - Eight-bit Thermometer Decoder
VerilogAnalyze the Verilog code for eight-bit thermometer decoder.
Complete the 5th SW→HW exercise
Find the correct schematic - Eight-bit Saturating Adder
VerilogAnalyze the Verilog code for eight-bit saturating adder.
Complete the 5th SW→HW exercise
Find the correct schematic - BCD Magnitude Comparator
VerilogAnalyze the Verilog code for bcd magnitude comparator.
Complete the 5th SW→HW exercise
Find the correct schematic - Five-input Majority Voter
VerilogAnalyze the Verilog code for five-input majority voter.
Complete the 5th SW→HW exercise
Find the correct schematic - One-hot Vector Analyzer
VerilogAnalyze the Verilog code for one-hot vector analyzer.
Complete the 5th SW→HW exercise