Chargement…
Chargement…
Start from software code and compare it with several RTL schematics. The goal is to choose the architecture that exactly preserves priorities, conditions, and registers.
0/9 exercises completed
Find the correct schematic - LFSR Stream Cipher
VerilogIdentify the feedback loop and output XOR of a synchronous stream cipher.
Find the correct schematic - Ones-complement Checksum
VerilogFind the accumulator that folds the most-significant carry before complementing the result.
Find the correct schematic - Period Counter
VerilogReconstruct edge detection and capture of a cycle counter between two events.
Find the correct schematic - PRBS Sequence Checker
VerilogAnalyze the Verilog code for prbs sequence checker.
Find the correct schematic - SRAM Byte-lane Mapper
VerilogAnalyze the Verilog code for sram byte-lane mapper.
Find the correct schematic - PS/2 Frame Validator
VerilogAnalyze the Verilog code for ps/2 frame validator.
Complete the 5th SW→HW exercise
Find the correct schematic - Reciprocal Frequency Estimator
VerilogAnalyze the Verilog code for reciprocal frequency estimator.
Complete the 5th SW→HW exercise
Find the correct schematic - Windowed Watchdog Decision
VerilogAnalyze the Verilog code for windowed watchdog decision.
Complete the 5th SW→HW exercise
Find the correct schematic - Eight-request Rotating Arbiter
VerilogAnalyze the Verilog code for eight-request rotating arbiter.
Complete the 5th SW→HW exercise