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Testbench: Dual-port RAM 128x16 (VHDL)

Validate

01

Objective

Verify writes on port A and independent reads on port B. Use self-checking controls and finish with final_report.

02

Operation

Inputs: i_we_a (1 bit), i_addr_a (7 bits), i_addr_b (7 bits), i_din_a (16 bits). Outputs: o_dout_b (16 bits).

Behavior

Synchronous operations occur on the rising edge of i_clk. Allow signal updates to settle before comparing outputs.
128x16 memory initialized to zero at elaboration, without reset. Synchronous write at i_addr_a if i_we_a=1; synchronous read at i_addr_b. The post-edge output is the pre-edge contents (read-first), including read/write collisions. Addresses A and B are independent.

Results

Ready to validate

Your testbench will run against the correct DUT and several hidden faults.

←Exercise list Next exerciseTestbench: Interrupt generator→

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Beginner
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Leaderboard

Testbench: Dual-port RAM 128x16 (VHDL)

Validate

01

Objective

Verify writes on port A and independent reads on port B. Use self-checking controls and finish with final_report.

02

Operation

Inputs: i_we_a (1 bit), i_addr_a (7 bits), i_addr_b (7 bits), i_din_a (16 bits). Outputs: o_dout_b (16 bits).

Behavior

Synchronous operations occur on the rising edge of i_clk. Allow signal updates to settle before comparing outputs.
128x16 memory initialized to zero at elaboration, without reset. Synchronous write at i_addr_a if i_we_a=1; synchronous read at i_addr_b. The post-edge output is the pre-edge contents (read-first), including read/write collisions. Addresses A and B are independent.

Results

Ready to validate

Your testbench will run against the correct DUT and several hidden faults.

←Exercise list Next exerciseTestbench: Interrupt generator→

Advanced