Blog
Careers
Community
Challenges
Leaderboard
FAQ
Contact
Report a problem

The Club

FR

CoursesView all→

Exercises→

Beginner
Intermediate
Advanced

Progress

Dashboard
Public profile
Badges
Daily quests
Leaderboard

2-to-1 multiplexer testbench (VHDL)

Validate

01

Objective

Test all eight combinations of i_d0, i_d1 and i_sel. The output must follow i_d0 when i_sel is 0 and i_d1 when i_sel is 1.

02

Operation

Behavior

The signal i_sel selects which path is forwarded to o_q.
When i_sel is 0, o_q follows i_d0; when it is 1, o_q follows i_d1.

Results

Ready to validate

Your testbench will run against the correct DUT and several hidden faults.

←Exercise list Next exercise4-bit counter testbench→

Beginner

Chargement…

>_FPGAPourTous

Learn VHDL, from beginner to expert.

Learn

All courses
All exercises
Write a testbench (VHDL)
Quizzes
Projects
Certification

Resources

FPGA and VHDL articles
Careers
Community
Challenges
Leaderboard

Help

FAQ
Contact
Report a problem

Legal information

Legal notice
Privacy
Terms of use