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VHDLBeginner

Testbench: NOR gate (VHDL)

Verify the low output when an input is active and the high idle output.

Exercise objective

The DUT applies the expected logic operation to its inputs and drives the result.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT applies the expected logic operation to its inputs and drives the result.

Skills you will practice

  • Truth Table
  • Operation

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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