VHDLBeginner
Testbench: Rising-edge detector (VHDL)
Verify that a one-cycle pulse appears only on a rising transition.
Exercise objective
The DUT detects a rising transition and produces a one-cycle pulse.
Prerequisites
- Read signals and write assertions in a VHDL testbench.
- Understand the circuit under test: The DUT detects a rising transition and produces a one-cycle pulse.
Skills you will practice
- Rising Edge
- Reset
Equipment and tools
- The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.