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VHDLBeginner

Testbench: Modulo-10 counter (VHDL)

Verify the decimal sequence and return to zero after nine.

Exercise objective

The DUT updates a counter according to the clock, reset and controls.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT updates a counter according to the clock, reset and controls.

Skills you will practice

  • Reset
  • Sequence
  • Wrap-around
  • Enable

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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