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VHDLBeginner

Testbench: Debounce filter (VHDL)

Verify that an input remains stable for several cycles before acceptance.

Exercise objective

The DUT performs the function described by this exercise.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT performs the function described by this exercise.

Skills you will practice

  • Stability
  • Latency

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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