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VHDLBeginner

Testbench: Traffic-light FSM (VHDL)

Verify cyclic state transitions and reset to the initial state.

Exercise objective

The DUT moves between states according to its inputs and produces the associated output.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT moves between states according to its inputs and produces the associated output.

Skills you will practice

  • State Transition
  • Reset

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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