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VHDLBeginner

Testbench: Register with priority clear (VHDL)

Verify clear priority over writes and the hold behavior.

Exercise objective

The DUT stores data on a clock edge with the specified controls.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT stores data on a clock edge with the specified controls.

Skills you will practice

  • Clear
  • Priority
  • Reset

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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