Testbench: 4-word synchronous FIFO (VHDL)

Objective

Verify FIFO order, empty, full and simultaneous operations. Use self-checking controls and finish with final_report.

Inputs: i_reset (1 bit), i_wr (1 bit), i_rd (1 bit), i_data (8 bits). Outputs: o_data (8 bits), o_empty (1 bit), o_full (1 bit).

Behavior

Synchronous operations occur on the rising edge of i_clk. Allow signal updates to settle before comparing outputs.
i_reset is active-high and asynchronous; it clears outputs and state unless another value is explicitly specified.
4x8 FIFO. Accept according to pre-edge state: write if not full, read if not empty. Synchronous read; o_data holds the last read value. Simultaneous requests: when empty only write, when full only read, otherwise both with unchanged occupancy. Reset empties the FIFO and clears o_data.

Chargement…