VHDLIntermediate
Testbench: One-shot generator (VHDL)
Verify a fixed-width pulse and ignored triggers while active.
Exercise objective
The DUT turns a trigger into a pulse of defined duration.
Prerequisites
- Read signals and write assertions in a VHDL testbench.
- Understand the circuit under test: The DUT turns a trigger into a pulse of defined duration.
Skills you will practice
- Pulse Width
- Busy
Equipment and tools
- The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.