Skip to main content
VHDLIntermediate

Testbench: Four-cycle stability filter (VHDL)

Verify acceptance latency and rejection of short changes.

Exercise objective

The DUT performs the function described by this exercise.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT performs the function described by this exercise.

Skills you will practice

  • Latency
  • Stability

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

Access the exercise

You unlock this exercise as you progress through the learning path. Club membership gives you access to the full path. Access to solutions and downloads depends on your account.

Sign inContinue the learning pathDiscover the Club