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VHDLIntermediate

Testbench: 8-bit priority encoder (VHDL)

Verify priority, validity and transitions between multiple requests.

Exercise objective

The DUT encodes the highest-priority request and indicates whether a request exists.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT encodes the highest-priority request and indicates whether a request exists.

Skills you will practice

  • Priority
  • Valid

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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