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VHDLIntermediate

Testbench: 4x8 register bank (VHDL)

Verify read, write, addressing and reserved-address protection.

Exercise objective

The DUT manages several registers accessible by address.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT manages several registers accessible by address.

Skills you will practice

  • Address
  • Write Enable

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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