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VHDLIntermediate

Testbench: Credit counter (VHDL)

Verify consume, return, boundary saturation and simultaneous events.

Exercise objective

The DUT tracks available credits and allows the corresponding operations.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT tracks available credits and allows the corresponding operations.

Skills you will practice

  • Credit
  • Boundary

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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