Testbench

Testbench: OR gate

Beginner

01Objective

Verify all four rows of an OR gate truth table. Use self-checking controls and finish with final_report. Perform at least 4 checks with check_output. Your testbench must pass on the correct DUT and detect hidden faults.

02Operation

Inputs: i_a (1 bit), i_b (1 bit). Outputs: o_q (1 bit).

Behavior

o_q applies OR to the inputs, without a clock.

Results

Ready to validate

Your testbench will run against the correct DUT and several hidden faults.

4-bit counter testbench Testbench: XOR gate

Beginner

Chargement…

>_FPGA For All

Learn VHDL, from beginner to expert.

Courses

VHDL
Verilog
SystemVerilog
FPGA
Hardware and PCB
Digital Electronics
Protocols
Zynq

Practice

All exercises
HW to simulation
VHDL specifications
Verilog specifications
Software to schematic
Block Design
Testbench
Leaderboard
Report a bug

Blog

FPGA & VHDL articles
Challenges
Certification
Community
FAQ

FAQ|Legal|Privacy|Contact||Terms

Testbench

Testbench: OR gate

Beginner

Validate

01Objective

Verify all four rows of an OR gate truth table. Use self-checking controls and finish with final_report. Perform at least 4 checks with check_output. Your testbench must pass on the correct DUT and detect hidden faults.

02Operation

Inputs: i_a (1 bit), i_b (1 bit). Outputs: o_q (1 bit).

Behavior

o_q applies OR to the inputs, without a clock.

Results

Ready to validate

Your testbench will run against the correct DUT and several hidden faults.

4-bit counter testbench Testbench: XOR gate

Beginner