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SystemVerilog is used here to verify Verilog circuits. The design under test (DUT) is provided: write a testbench with stimulus and self-checking assertions.
0/10 exercises completed
Testbench: Synchronous FIFO
SystemVerilogVerify ordering, empty/full flags and simultaneous operations.
Testbench: Single-port RAM 256x8
SystemVerilogVerify synchronous writes and reads at several addresses.
Testbench: Dual-port RAM 128x16
SystemVerilogVerify writes on port A and independent reads on port B.
Testbench: Interrupt generator
SystemVerilogVerify pulse width and interrupt-vector capture in the status register.
Testbench: UART transmitter
SystemVerilogVerify start, data and stop bits together with the busy signal.
Testbench: Tick-driven stopwatch timer
SystemVerilogVerify reset, loading, countdown and the completion pulse.
Complete Testbench: UART transmitter
Testbench: Memory arbiter
SystemVerilogVerify rotating priority, one-hot grants and respect for backpressure.
Complete Testbench: Tick-driven stopwatch timer
Testbench: Signed multiplier
SystemVerilogVerify signed products, zero and representable boundaries.
Complete Testbench: Memory arbiter
Testbench: Modulo-m adder-subtractor
SystemVerilogVerify sum and difference reduction within the modulo interval.
Complete Testbench: Signed multiplier
Testbench: Nonrestoring divider
SystemVerilogVerify quotient, remainder and explicit division-by-zero behavior.
Complete Testbench: Modulo-m adder-subtractor