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SystemVerilog is used here to verify Verilog circuits. The design under test (DUT) is provided: write a testbench with stimulus and self-checking assertions.
0/20 exercises completed
Testbench: 4-way round-robin arbiter
SystemVerilogVerify priority rotation after each grant and the no-request case.
Testbench: 4-word synchronous FIFO
SystemVerilogVerify FIFO order, empty, full and simultaneous operations.
Testbench: Valid/ready buffer
SystemVerilogVerify data preservation under backpressure and recovery.
Testbench: Two-cycle latency pipeline
SystemVerilogVerify exact latency and ordering of multiple transactions.
Testbench: Configurable 8-bit PWM
SystemVerilogVerify duty cycle, configuration reload and boundaries.
Testbench: Simplified UART transmitter
SystemVerilogVerify start bit, eight data bits and stop bit at the requested baud tick.
Complete Testbench: Configurable 8-bit PWM
Testbench: SPI mode-0 transmitter
SystemVerilogVerify clock edges, MSB-first order and transaction completion.
Complete Testbench: Simplified UART transmitter
Testbench: Watchdog with service pulse
SystemVerilogVerify timeout, service and alarm output.
Complete Testbench: SPI mode-0 transmitter
Testbench: One-shot generator
SystemVerilogVerify a fixed-width pulse and ignored triggers while active.
Complete Testbench: Watchdog with service pulse
Testbench: Four-cycle stability filter
SystemVerilogVerify acceptance latency and rejection of short changes.
Complete Testbench: One-shot generator
Testbench: 1101 sequence detector
SystemVerilogVerify overlap, partial overlap and absence of false positives.
Complete Testbench: Four-cycle stability filter
Testbench: 4-bit CRC calculator
SystemVerilogVerify CRC results on several words and reset between frames.
Complete Testbench: 1101 sequence detector
Testbench: 8-bit priority encoder
SystemVerilogVerify priority, validity and transitions between multiple requests.
Complete Testbench: 4-bit CRC calculator
Testbench: 4x8 register bank
SystemVerilogVerify read, write, addressing and reserved-address protection.
Complete Testbench: 8-bit priority encoder
Testbench: Synchronous reset controller
SystemVerilogVerify asynchronous reset assertion and release after two clock edges.
Complete Testbench: 4x8 register bank
Testbench: Credit counter
SystemVerilogVerify consume, return, boundary saturation and simultaneous events.
Complete Testbench: Synchronous reset controller
Testbench: Packet-length checker
SystemVerilogVerify start, counting, early end and correct length.
Complete Testbench: Credit counter
Testbench: Baud tick generator
SystemVerilogVerify division, reload and the exactly periodic pulse.
Complete Testbench: Packet-length checker
Testbench: Simple dual-port memory
SystemVerilogVerify writes, reads and independence of both ports.
Complete Testbench: Baud tick generator
Testbench: Handshake controller
SystemVerilogVerify valid/ready, data hold and transaction completion.
Complete Testbench: Simple dual-port memory