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Block Design

Filtered ADC Stream to DMA

Chain an ADC stream, AXI-Stream FIFO, FIR filter and DMA writer to DDR.

Exercise objective

Chain an ADC stream, AXI-Stream FIFO, FIR filter and DMA writer to DDR.

Prerequisites

  • Read digital schematics and recognize clocks, resets and interfaces.
  • Identify the blocks and interfaces needed for “Filtered ADC Stream to DMA”.

Skills you will practice

  • Chain an ADC stream, AXI-Stream FIFO, FIR filter and DMA writer to DDR.
  • FPGA
  • Block Design
  • Vivado
  • IP Integrator

Equipment and tools

  • Browser-based Block Design editor.

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