06
SPI Sensor to Display
Trigger an SPI read, convert the measurement and display the low digit on 7 segments.
IP IntegratorLocked
Chargement…
Chargement…
Assemble predefined IP blocks in a Vivado-like canvas, then validate the topology and interconnected ports.
Type
BD
Done
0
Unlocked
5
Total
34
Build a minimal block design: the board clock drives a BCD counter, then the counter drives a 7-segment display.
Assemble a slowed clock, a chaser controller and an 8-bit LED output.
Filter push buttons, generate a pulse and increment a counter shown on a 7-segment display.
Load a setpoint from switches, drive a PWM generator and route the signal to an LED.
Assemble an RX-to-TX path with a baud-rate generator and an intermediate buffer.
Trigger an SPI read, convert the measurement and display the low digit on 7 segments.
Read an I2C sensor, scale the measurement and drive a fan with PWM.
Combine a divider, a timer and an FSM to drive vehicle and pedestrian lights.
Receive UART bytes, buffer them, compute a CRC-8 and transmit the extended packet.
Connect an AXI-Lite master to a register bank driving PWM and LEDs.
Assemble a simplified Zynq system with reset, AXI interconnect, timer and two GPIO blocks.
Connect two AXI masters to the crossbar, then route the output to a DDR manager.
Chain an ADC stream, AXI-Stream FIFO, FIR filter and DMA writer to DDR.
Route a Wishbone master to AXI-Lite registers driving GPIO and PWM.
Assemble a camera, line buffer, overlay and HDMI controller chain.
Assemble a small SoC: MU0 CPU, address decoder, ROM, RAM, IRQ timer and GPIO.
Build the recommended minimal MicroBlaze subsystem with LMB, UART, timer and interrupt controller.
Aggregate timer and GPIO interrupts in an AXI INTC before presenting them to the PS.
Recreate AMD’s debug design: JTAG transactions to BRAM with AXI interface monitoring.
Let a Zynq and an AXI Traffic Generator access two independent ports of the same BRAM.
Integrate a packaged IP with control registers, PWM, status and interrupt.
Configure an AXI DMA in simple mode: DDR read, AXI4-Stream FIFO, then DDR writeback.
Safely cross from a 100 MHz to a 150 MHz domain using Clock Converter and Data FIFO.
Offload a DDR-to-DDR copy to AXI Central DMA under PS control.
Arbitrate two AXI Traffic Generators toward a BRAM and a GPIO.
Share a BRAM mailbox between the processor and a PL state machine with interrupt.
Generate DDR traffic and measure bandwidth, latency and transactions on the AXI path.
Read samples from DDR, stream them over AXI4-Stream and drive an I2S codec.
Build a DDR ↔ AXI DMA ↔ AXI Ethernet ↔ RGMII PHY packet path.
Monitor an intentionally faulty AXI-Lite slave and expose the checker assertion.
Connect MicroBlaze instruction and data buses to DDR4 through the UltraScale Memory IP.
Expose BRAM and AXI-Lite registers to a PCIe host through XDMA.
Safely isolate an AXI region before partial loading through DFX Controller and ICAP.
Inject PL AXI traffic into the Versal NoC through to the integrated DDRMC.