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Block Design

Memory-Mapped MU0 System

Assemble a small SoC: MU0 CPU, address decoder, ROM, RAM, IRQ timer and GPIO.

Exercise objective

Assemble a small SoC: MU0 CPU, address decoder, ROM, RAM, IRQ timer and GPIO.

Prerequisites

  • Read digital schematics and recognize clocks, resets and interfaces.
  • Identify the blocks and interfaces needed for “Memory-Mapped MU0 System”.

Skills you will practice

  • Assemble a small SoC: MU0 CPU, address decoder, ROM, RAM, IRQ timer and GPIO.
  • FPGA
  • Block Design
  • Vivado
  • IP Integrator

Equipment and tools

  • Browser-based Block Design editor.

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