Block Design
AXI DMA Stream Loopback
Configure an AXI DMA in simple mode: DDR read, AXI4-Stream FIFO, then DDR writeback.
Exercise objective
Configure an AXI DMA in simple mode: DDR read, AXI4-Stream FIFO, then DDR writeback.
Prerequisites
- Read digital schematics and recognize clocks, resets and interfaces.
- Identify the blocks and interfaces needed for “AXI DMA Stream Loopback”.
Skills you will practice
- Configure an AXI DMA in simple mode: DDR read, AXI4-Stream FIFO, then DDR writeback.
- DMA
- AXI4-Stream
- DDR
- IP Integrator
Equipment and tools
- Browser-based Block Design editor.
- Zynq UltraScale+; AXI DMA Direct Register Mode with SG disabled.