Block Design
HP Port Benchmark with AXI Performance Monitor
Generate DDR traffic and measure bandwidth, latency and transactions on the AXI path.
Exercise objective
Generate DDR traffic and measure bandwidth, latency and transactions on the AXI path.
Prerequisites
- Read digital schematics and recognize clocks, resets and interfaces.
- Identify the blocks and interfaces needed for “HP Port Benchmark with AXI Performance Monitor”.
Skills you will practice
- Generate DDR traffic and measure bandwidth, latency and transactions on the AXI path.
- Performance
- AXI
- DDR
- IP Integrator
Equipment and tools
- Browser-based Block Design editor.
- Zynq UltraScale+; AXI Performance Monitor with one monitor slot.