Block Design
RGMII Ethernet with AXI DMA
Build a DDR ↔ AXI DMA ↔ AXI Ethernet ↔ RGMII PHY packet path.
Exercise objective
Build a DDR ↔ AXI DMA ↔ AXI Ethernet ↔ RGMII PHY packet path.
Prerequisites
- Read digital schematics and recognize clocks, resets and interfaces.
- Identify the blocks and interfaces needed for “RGMII Ethernet with AXI DMA”.
Skills you will practice
- Build a DDR ↔ AXI DMA ↔ AXI Ethernet ↔ RGMII PHY packet path.
- Ethernet
- RGMII
- DMA
- IP Integrator
Equipment and tools
- Browser-based Block Design editor.
- Zynq UltraScale+ with RGMII PHY and board-correct Ethernet clocks.