Block Design
Catch a Violation with AXI Protocol Checker
Monitor an intentionally faulty AXI-Lite slave and expose the checker assertion.
Exercise objective
Monitor an intentionally faulty AXI-Lite slave and expose the checker assertion.
Prerequisites
- Read digital schematics and recognize clocks, resets and interfaces.
- Identify the blocks and interfaces needed for “Catch a Violation with AXI Protocol Checker”.
Skills you will practice
- Monitor an intentionally faulty AXI-Lite slave and expose the checker assertion.
- AXI
- Verification
- Debug
- IP Integrator
Equipment and tools
- Browser-based Block Design editor.
- AMD FPGA with JTAG; checker configured for 32-bit AXI4-Lite.