AXI4-Lite Master

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01General Operation

The module converts user requests (i_go, i_rnw, i_address, i_data_in) into AXI4-Lite transactions. For writes, AW, W, and B channels are managed. For reads, AR and R channels. The module signals transaction completion and read data.

Generics: G_AXI_DATA_WIDTH (default 32), G_AXI_ADDR_WIDTH (default 32)
Configurable strobe via G_AXI_STRB_PASSTHROUGH

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_rst`	Input	1 bit	Synchronous active-high reset
`i_go`	Input	1 bit	Start transaction
`i_rnw`	Input	1 bit	'1' = read, '0' = write
`o_done`	Output	1 bit	Transaction done pulse
`i_address`	Input	G_AXI_ADDR_WIDTH bits	Target address
`i_data_in`	Input	G_AXI_DATA_WIDTH bits	Write data
`i_wr_strb`	Input	G_AXI_DATA_WIDTH/8 bits	Write strobe
`o_data_out`	Output	G_AXI_DATA_WIDTH bits	Read data
`m00_axi_*`	—	—	AXI4-Lite master signals (aw, w, b, ar, r)

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