VHDL

Follow the courses in the recommended order.

1. 01
   Introduction to VHDLWhat is VHDL, its history, and why use it for FPGAs?
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2. 02
   VHDL File ArchitectureThe two fundamental blocks: the entity and the architecture.
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3. 03
   Combinational and Sequential LogicThe fundamental distinction between combinational logic (no memory) and sequential logic (clocked).
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4. 04
   Data TypesVHDL fundamental types: std_logic, std_logic_vector, integer, unsigned, signed.
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5. 05
   OperatorsLogical, relational, arithmetic, and shift operators in VHDL.
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6. 06
   Signals, Variables, and ConstantsThe three ways to store a value in VHDL: signal, variable, and constant — differences and usage.
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7. 07
   Best PracticesNaming conventions, prefixes, and best practices for readable and maintainable VHDL code.
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8. 08
   The Process BlockThe process block: sensitivity list, sequential statements, and combinational/sequential patterns.
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9. 09
   Examples: MUX 4→1Complete implementation of a 4-to-1 multiplexer in different VHDL styles.
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10. 10
    Testbenches and SimulationWriting VHDL testbenches to verify your circuit behavior before synthesis.
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11. 11
    State Machines (Mealy/Moore)Design and implementation of Finite State Machines (FSM) in VHDL: Moore and Mealy.
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12. 12
    Advanced VHDL ConceptsAttributes, functions, packages, procedures, subtypes and pipelining — taking VHDL to the next level.
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13. 13
    Vivado and Other FPGA ToolsOverview of FPGA development tools — proprietary and open-source: Vivado, Quartus Prime, Libero SoC, and open alternatives.
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14. 14
    Components & InstantiationDesigning structural architectures in VHDL: component declarations, port map, generic map, and direct instantiation.
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