Chargement…
Chargement…
Start from a technical specification and design the complete VHDL, validated by GHDL simulation.
Exercises
27
Done
0
Total
27
Full SPI Master (Configurable mode)
Implement a generic SPI master controller supporting all 4 SPI modes, with clock divider, multi-slave and configurable frame sizes.
UART 8N1 Transmitter
Implement a complete UART 8N1 transmitter with baud rate generator and 4-state FSM driving the serial transfer.
Configurable Synchronous FIFO
Implement a synchronous FIFO with configurable width and depth, circular pointers and full/empty flags.
Single-Port RAM 256x8
Implement a single-port synchronous RAM of 256 words of 8 bits with synchronous read and synchronous write.
Dual-Port RAM 128x16
Implement a dual-port synchronous RAM of 128 words of 16 bits. Port A writes, port B reads.
Interrupt Generator
Implement an interrupt generator: each IT vector stays active for g_MIN_WIDTH_PULSE cycles then is reported in the status register.
AXI4-Lite Master
Implement a generic AXI4-Lite master capable of performing read and write accesses on an AXI4-Lite bus.
AXI4-Lite Slave
Implement a generic AXI4-Lite slave with simplified register interface.
AXI4 Master - Write Channels
Implement a simple AXI4 master managing the three write channels: Write Address (AW), Write Data (W) and Write Response (B).
mu0 Processor (16-bit)
Implement a 16-bit accumulator-based mini processor: ALU, PC/IR/ACC/R registers, control FSM, and top-level assembly. 14 instructions covered.
SHA-256 core (1-block)
Implement a hardware SHA-256 core on a 512-bit block: logical functions, message schedule shift register, compression unit and top-level FSM.
4-Bit SAR ADC Controller
Implement a successive-approximation conversion FSMD to drive an internal DAC and read a comparator.
2-Stage float32 Multiplier
Implement a simplified IEEE-754 single-precision multiplier with mantissa/exponent split.
Intel HEX Initialized ROM
Build a simulation ROM from Intel HEX records provided by the project.
µ-law Audio Compressor
Develop a functional µ-law compression model for a normalized real-valued signal.
Dual Edge Flip Flop
Model a simple DDR output from two opposite-edge registers.
Stopwatch Timer
Build a decimal seconds/tenths stopwatch driven by an external tick.
Asynchronous FIFO
Implement a small 8-bit FIFO between two clock domains.
IIR Biquad Filter
Implement an integer IIR biquad cell with fixed coefficients.
Decimation Filter
Average four samples then output one decimated sample.
Memory Arbiter
Arbitrate two masters onto a single memory port.
Bubble Sort Engine
Sort four 4-bit values with a comparator network inspired by bubble sort.
Merge Sorted Streams
Merge two already-sorted pairs into four sorted outputs.
Median Calculator
Compute the median of five 4-bit values.
1D Convolution Engine
Implement a 3-tap 1D convolution with fixed coefficients `1,2,1`.
Matrix Transpose
Transpose a 2x2 byte matrix packed into 32 bits.
Longest Consecutive Sequence
Measure the longest `+1` run in four already-sorted values.