Protocols

AXI, AXI-Lite, AXI-Stream and other FPGA and SoC interconnect interfaces.

1. 01AXI ProtocolThe AXI (Advanced eXtensible Interface) protocol by ARM: write/read channels, burst transfers and handshake.Read
2. 02AXI-Lite ProtocolAXI-Lite: the simplified AXI variant for configuration registers and control interfaces.Read
3. 03AXI4-Stream: TVALID, TREADY, TLAST, and TKEEPLearn AXI4-Stream handshaking and continuous data transfer with TVALID, TREADY, TLAST, and TKEEP, without address management.Read
4. 04SPI ProtocolSPI signal lines, transfer modes, frames and VHDL implementation points.Read
5. 05I2C ProtocolI2C addressing, ACK/NACK, START/STOP conditions and VHDL FSM structure.Read
6. 06UART ProtocolUART framing, baud-rate generation, oversampling and VHDL implementation points.Read
7. 07Wishbone Bus Protocol: Signals, ACK, Pipelining, and VHDLLearn the Wishbone bus protocol, its master-slave signals and ACK handshake, pipelined transfers, VHDL implementation, and differences from AXI.Read
8. 08Avalon ProtocolAvalon-MM/Avalon-ST signals, handshakes and Platform Designer integration.Read