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FPGA VHDL
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Protocols
8 courses
Follow the courses in the recommended order.
01
AXI Protocol
The AXI (Advanced eXtensible Interface) protocol by ARM: write/read channels, burst transfers and handshake.
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02
AXI-Lite Protocol
AXI-Lite: the simplified AXI variant for configuration registers and control interfaces.
Read
03
AXI-Stream Protocol
AXI-Stream: continuous data streaming without address management.
Read
04
SPI Protocol
SPI signal lines, transfer modes, frames and VHDL implementation points.
Read
05
I2C Protocol
I2C addressing, ACK/NACK, START/STOP conditions and VHDL FSM structure.
Read
06
UART Protocol
UART framing, baud-rate generation, oversampling and VHDL implementation points.
Read
07
Wishbone Protocol
Wishbone bus signals, ACK handshake, pipeline mode and comparison with AXI.
Read
08
Avalon Protocol
Avalon-MM/Avalon-ST signals, handshakes and Platform Designer integration.
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