I2C Master - Start & Addressing

Simplified I2C waveform generator that emits an address phase: START, a 7-bit address, the R/W bit, an ACK slot, then a return to idle.

Behaviour:

• While idle, o_sda and o_scl are '1'.
• If i_start='1' on a rising edge of i_clk, the module stores i_addr & i_rw and generates START by pulling o_sda low while o_scl remains high.
• The eight stored bits are emitted MSB first as o_scl toggles.
• State ST_ACK represents the ninth clock slot, but no external ACK is sampled: o_sda is an output and the module has no SDA input.
• o_done is '1' for one cycle; returning to idle then restores o_sda and o_scl to '1' and ends the sequence.

*The module has no reset input; its registers rely on their initialization values.*