Chargement…
Chargement…
Simplified I2C master handling an address write transaction. The module generates the START condition (SDA falls while SCL is high), then transmits 8 bits (7-bit address + R/W bit) serially, waits for slave acknowledgment, and signals transaction completion.
Reset is asynchronous and active-high.
| Signal | Direction | Width | Description |
|---|---|---|---|
i_clk | Input | 1 bit | System clock |
i_start | Input | 1 bit | Transaction trigger |
i_addr | Input | 7 bits | Slave address |
i_rw | Input | 1 bit | R/W bit (0=write, 1=read) |
o_sda | Output | 1 bit | SDA line |
o_scl | Output | 1 bit | SCL line |
o_done | Output | 1 bit | Transaction complete |