I2C Master - Start & Addressing

Beginner

00:00

01General Operation

Simplified I2C master performing a single address-write transaction (START + 7-bit address + R/W bit + ACK + STOP).

Behaviour:

Idle: o_sda and o_scl held high (released lines).
On i_start='1', the module issues a START: o_sda falls while o_scl is high.
Serial transmission of i_addr (7 bits, MSB first) then the i_rw bit, on falling edges of o_scl.
The 9th cycle releases o_sda and samples the slave ACK.
STOP generated: o_sda rises while o_scl is high, then o_done ← '1'.

*Asynchronous active-high reset.*

02Interface

Signal	Direction	Width	Description
`i_clk`	Input	1 bit	System clock
`i_start`	Input	1 bit	Transaction trigger
`i_addr`	Input	7 bits	Slave address
`i_rw`	Input	1 bit	R/W bit (0=write, 1=read)
`o_sda`	Output	1 bit	SDA line
`o_scl`	Output	1 bit	SCL line
`o_done`	Output	1 bit	Transaction complete

Chargement…