Skip to main content
VHDLAdvanced

Testbench: Tick-driven stopwatch timer (VHDL)

Verify reset, loading, countdown and the completion pulse.

Exercise objective

The DUT counts cycles until the expected event and reports its state.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT counts cycles until the expected event and reports its state.

Skills you will practice

  • Reset
  • Done
  • Load
  • Boundary

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

Access the exercise

You unlock this exercise as you progress through the learning path. Club membership gives you access to the full path. Access to solutions and downloads depends on your account.

Sign inContinue the learning pathDiscover the Club