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VHDLAdvanced

Testbench: Modulo-m adder-subtractor (VHDL)

Verify sum and difference reduction within the modulo interval.

Exercise objective

The DUT reduces a sum or difference to a modulo interval.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT reduces a sum or difference to a modulo interval.

Skills you will practice

  • Operation
  • Difference
  • Boundary

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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