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Testbench: OR gate (VHDL)

Validate

01

Objective

Verify all four rows of an OR gate truth table. Use self-checking controls and finish with final_report.

02

Operation

Inputs: i_a (1 bit), i_b (1 bit). Outputs: o_q (1 bit).

Behavior

o_q applies OR to the inputs, without a clock.

Results

Ready to validate

Your testbench will run against the correct DUT and several hidden faults.

←Exercise list Next exerciseTestbench: XOR gate→

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