VHDLBeginner
Testbench: Inverter gate (VHDL)
Verify that the output is inverted for both input values.
Exercise objective
The DUT inverts the logic level of its input.
Prerequisites
- Read signals and write assertions in a VHDL testbench.
- Understand the circuit under test: The DUT inverts the logic level of its input.
Skills you will practice
- Truth Table
- Inversion
Equipment and tools
- The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.