Skip to main content
VHDLBeginner

Testbench: 4-bit enabled register (VHDL)

Verify asynchronous reset, capture and hold while enable is disabled.

Exercise objective

The DUT stores data on a clock edge with the specified controls.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT stores data on a clock edge with the specified controls.

Skills you will practice

  • Reset
  • Enable

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

Access the exercise

You unlock this exercise as you progress through the learning path. Club membership gives you access to the full path. Access to solutions and downloads depends on your account.

Sign inContinue the learning pathDiscover the Club