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VHDLBeginner

Testbench: Serial shift register (VHDL)

Verify serial insertion and bit progression across several edges.

Exercise objective

The DUT shifts serially received bits on each clock edge.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT shifts serially received bits on each clock edge.

Skills you will practice

  • Reset
  • Sequence
  • Enable

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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