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VHDLBeginner

Testbench: Enabled D flip-flop (VHDL)

Verify rising-edge capture and hold when enable is low.

Exercise objective

The DUT stores input D on a rising edge when enabled.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT stores input D on a rising edge when enabled.

Skills you will practice

  • Clock
  • Enable
  • Reset

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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