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VHDLBeginner

Testbench: 4-bit LFSR (VHDL)

Verify the pseudo-random sequence and the non-zero state after reset.

Exercise objective

The DUT generates a pseudo-random sequence from its internal state.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT generates a pseudo-random sequence from its internal state.

Skills you will practice

  • Sequence
  • Non-zero
  • Reset
  • Enable

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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