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VHDLBeginner

Testbench: 4-bit accumulator (VHDL)

Verify conditional addition, hold and modulo overflow.

Exercise objective

The DUT accumulates enabled values across clock edges.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT accumulates enabled values across clock edges.

Skills you will practice

  • Enable
  • Sum
  • Wrap-around
  • Reset

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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