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VHDLBeginner

Testbench: 4-bit saturating adder (VHDL)

Verify saturation at fifteen instead of wrap-around.

Exercise objective

The DUT adds two words without exceeding the maximum representable value.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT adds two words without exceeding the maximum representable value.

Skills you will practice

  • Saturation
  • Boundary
  • Carry

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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