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VHDLBeginner

Testbench: 8-bit parity generator (VHDL)

Verify even, odd and extreme data words.

Exercise objective

The DUT calculates the parity bit for the presented value.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT calculates the parity bit for the presented value.

Skills you will practice

  • Parity
  • Boundary

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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