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VHDLIntermediate

Testbench: Simplified UART transmitter (VHDL)

Verify start bit, eight data bits and stop bit at the requested baud tick.

Exercise objective

The DUT serializes data according to the expected UART format.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT serializes data according to the expected UART format.

Skills you will practice

  • Start Bit
  • Data Bits
  • Stop Bit

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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