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VHDLIntermediate

Testbench: Watchdog with service pulse (VHDL)

Verify timeout, service and alarm output.

Exercise objective

The DUT monitors a timeout and reports a missing service pulse.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT monitors a timeout and reports a missing service pulse.

Skills you will practice

  • Timeout
  • Service
  • Reset

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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