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VHDLIntermediate

Testbench: Synchronous reset controller (VHDL)

Verify asynchronous reset assertion and release after two clock edges.

Exercise objective

The DUT filters and synchronizes reset release to the clock.

Prerequisites

  • Read signals and write assertions in a VHDL testbench.
  • Understand the circuit under test: The DUT filters and synchronizes reset release to the clock.

Skills you will practice

  • Reset
  • Latency

Equipment and tools

  • The VHDL editor and validation are available in the browser. You do not need an FPGA board for this exercise.

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